ABSTRACT
Non-invasive IC Tomography Using Spatial Correlations
. by
Davood Shamsi
We introduce a new methodology for post-silicon characterization of the gate-
level variations in a manufactured Integrated Circuit (IC). The estimated char-
acteristics are based on the power and the delay measurements that are affected
by the process variations. The power (delay) variations are spatially correlated.
Thus, there exists a basis in which variations are sparse. The sparse representa-
tion suggests using the Ll-regularization (the compressive sensing theory). We
show how to use the compressive sensing theory to improve post-silicon charac-
terization. We also address the problem by adding spatial constraints directly to
the traditional L2-minimization.
The proposed methodology is fast, inexpensive, non-invasive, and applicable
to legacy designs. Noninvasive IC characterization has a range of emerging ap-
plications, including post-silicon optimization, IC identification, and variations’
modeling∕simulations. The evaluation results on standard benchmark circuits
show that, in average, the gate level characteristics estimation accuracy can be
improved by more than two times using the proposed methods.
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