The name is absent

Pre-Silicon optimizations (gate sizing) and post-silicon optimizations (adap-
tive body bias) can be used to reduce the loss of the parametric yield. Mani
et al. [52] propose a joint optimization method to mitigate effects of varia-
tions on the yield. They show that their method results in a reduction of
5-35% in the leakage current.

In all the mentioned post-silicon optimization methods, an estimation of
variations is necessary to optimize each circuit separately. Our method can
efficiently provide them such an estimation.

3. Manufacturing process characterization: The proposed variations estima-
tion method can be used to characterize the statistical properties of a spe-
cific manufacturing technique. In the other words, one can characterize
variations based on the specific manufacturing technology. This characteri-
zation can be used to optimize designs for a specific manufacturing technol-
ogy. It can also be used to modify the manufacturing technology in order
to decrease variations.

4. IC identification and finger printing: Variations are result of complicated
nanoscale physical interactions and systematic imperfectness of the manu-
facturing tools. Thus, it is practically impossible to clone variations in an
IC; i.e., the variations in each IC are unique and can not be replicated. It
is an important property that can be used in IC identification and finger
printing.

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