6.3.2 Delay tomography results
To evaluate the performance of the proposed methods, we simulate the variation
model (Section 4.1.1) on a number of MCNC benchmark circuits. A total of 12%
random variations is assumed. Correlated intra-die variation is 60% of the total
variation [16] [76] ; 20% of the total variation is uncorrelated intra-die variation
and the remaining variation is allotted to the inter-die variation.
Similar to Section 6.2, we have used SIS software to map the benchmark
circuits to NAND2, NAND3, NAND4, NOR2, NOR3, NOR4, and inverter gates.
Then, using Dragon, a placement software package [1], gates are placed on the IC.
Since various gates cover different areas on the IC, gates are located on irregular
grids.
To calculate the falling and rising coefficients (ξ∕,3u and ξ,sffu in Equation 4.7),
we implemented all the gates with 65nm CMOS transistor technology. Then, we
used the HSPICE software to fit the linear model for all gates.
Figure 6.5 shows variations estimation error for the /^-minimization and the
∕1-regularization methods. The horizontal axis is delay measurement noise and
the vertical axis is variations estimation error. The /ɪ-regularization yields more
than a 50% decrease in error over the /^-minimization. The estimation subspace
is 84 for both C432 and C880 circuits. When measurement noise is small, delay
measurements provides enough information to estimate variations accurately. As
measurement noise increase, sparsity does not provide significant information.
76
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