The name is absent

variation sparsity in the power framework.

3.3.2 Regular grid tomography

First, we assume that the logic gates are located on a regular T × R grid on
the chip. The matrix of process variation on the regular grid is denoted by
H = {h_Stt}s=i...T,t=i...R, where h_s,_t is variation of the gate located in the (s, t)-th
point of the grid. We stack all the elements of the matrix H in a long column
vector d. Assume W is the transformation matrix for a wavelet in which variation
vector d is sparse. Let

s = Wd;                            (3.6)

then, s is a sparse vector.

Using the wavelet basis to model the spatial correlation of the process varia-
tion, Equation 3.4 becomes

p = Ad + e = AW¹s + e.                 (3.7)

The sparse s can be recovered using the optimization in Equation 2.4:

min ∣∣s∣∣ι + Λ∣∣AW¹s — y∣∣2∙                     (3.8)

The process variation d is then recovered using d = Ws.

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