Chapter 4
Delay Tomography
In this chapter, we extend the variation estimation to the delay framework. Sim-
ilar to the power tomography in Chapter 3, we only use primary inputs∕outputs
of the IC to characterize the delay variations. The approach is based on our
paper in ICCAD 2008 conference [63].
4.1 Preliminaries
4.1.1 Delay variation model
Transition delay is usually modeled as a linear function of transistor feature size
variations [38,49,58]. For example, consider a NAND2 gate where one of its
inputs is 1 and the other input, at time t = 0, transits from 0 to 1. Because of
propagation delay, the output transits from 1 to 0 at time t = dr. When there
38
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