The name is absent

are variations in transistor feature size, rising propagation delay, d_r, varies among
different NAND2 gates in the IC. i.e. [49]

⅛(^^otal) = (/nominal _{+ ξ}^total                 (4.₁)

where ξ is a constant and (/nominal j_s ^}_ιe nominal rising delay of the gate. Note
that, even if we model the propagation delay quadratic (or higher order) [29], we
can use the same approach by assuming new variables for higher order parameters.

4.1.2 Sensitizable paths

A path in an IC is defined as a sequence of logic gates from an input of the
IC to one of its output pins. To find propagation delay in a path, one should
find an appropriate input vector for the IC. The input vector should guarantee
propagation of a transition in the path. If such an input vector exists, the path
is called sensitizable-, otherwise it is called Unsensitizable.

4.1.3 Global flow of the delay tomography

Figure 4.1 shows the global flow of the work. At the first step, we feed the circuit
with a number of input vector pairs based on the set of sensitizable paths. The
inputs are found based on the path selection procedure introduced in Section
4.5. In step 2, propagation delay is measured for every sensitizable path. Based
on the measured propagation delays, we construct a System of Linear Equations

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