pendent measurements, the ^-minimization method performs poorly. However,
it is widely known that variations (power or delay) are spatially correlated; i.e.,
nearby gates are expected to have close variations. Because of the spatial correla-
tions in the variations, there exists a basis in which variations can be represented
sparsely. The sparse representation suggests using the compressive sensing theory.
We show how to use the compressive sensing theory to improve the post-silicon
characterization. We also modify the traditional ^-minimization by adding the
spatial constraint directly. The spatial constraints enforce the nearby gates to
have close variations. The proposed method just uses external input∕output pins
of the IC for the estimation. In the power framework, first, a number of input
vectors are applied to the IC and power consumption is measured for each input
vector. Next, we establish an optimization problem based on the power measure-
ments. Finally, we improve the optimization problem using spatial correlation in
variations. In the delay framework, we follow the same procedure as we did in
the power framework. However, one can measure paths delays just in sensitizable
paths. Thus, here, the optimization problem is constructed based on the delay
measurements in a set of testable basis paths.
The variations can affect various properties in the IC and estimating variations
in an IC suggests a number of applications such as post-silicon optimizations.
Evaluation results verify our method. We showed that, compared to traditional
^-minimization, ^ɪ-regularization can improve variation estimation about 80%
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