Yuanbin Guo et al.
17
7. CONCLUSION
In this paper, we propose an efficient circulant MIMO chip
equalizer for multicode CDMA downlink by using FFT-
based operations to avoid the direct matrix inverse. A
comparative study demonstrates very promising perfor-
mance/complexity tradeoff. VLSI-oriented optimizations
are proposed to reduce the number and complexity of FFTs.
The inverse of (4 × 4) submatrices is solved by partitioned
(2 × 2) submatrices, which leads to dramatically simplified
VLSI modules. The VLSI design space is explored extensively
for area/time efficiency by a Catapult C-based HLS method-
ology. The VLSI design is validated in a real-time FPGA
prototyping system.
ACKNOWLEDGMENTS
The authors would like to thank Dr. Behnaam Aazhang and
the anonymous reviewers for their instructive comments.
Joseph R. Cavallaro was supported in part by NSF under
Grants ANI-9979465, EIA-0224458, and EIA-0321266.
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