Implementation of a 3GPP LTE Turbo Decoder Accelerator on GPU

TABLE III: Throughput vs W

improves the BER performance of the decoder significantly.
Therefore, full-log-MAP is a better choice for this design.

C. Architecture Comparison

Table IV compares our decoder with other programmable turbo
decoders. Our decoder with W = 64 compares favorably in
terms of throughput and BER performance. We can support both
the full-log-MAP (FLM) algorithm and the simplified max-log-
MAP (MLM) algorithm while most other solutions only support
the sub-optimal max-log-MAP algorithm.

TABLE IV: Our decoder vs other programmable turbo decoders

VI. Conclusion

In this paper, we presented a 3GPP LTE compliant turbo
decoder implemented on GPU. We portion the workload across
cores on the GPU by dividing the codeword into many sub-
blocks to be decoded in parallel. Furthermore, all computation
is completely parallel for each sub-block. To reduce the memory
bandwidth needed to keep the cores fed, we prefetch data into
shared memory and keep immediate data in shared memory.
As different sub-block sizes can lead to BER performance
degradation, we presented how both BER performance and
throughput is affected by sub-block size. We show that our
decoder provides faster throughput even though the full-log-
MAP algorithm is used. As the decoder is done in software, we
can easily change the QPP interleaver and trellis structure states
to support other codes. Future work includes other partitioning
and memory strategies to improve throughput of the decoder.
Furthermore, we will implement a completely iterative MIMO
receiver by combining this decoder with a MIMO detector on
the GPU.

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