The name is absent

66

B.l FPGA circuit

The FPGA circuit provides the digital logic to control every SLM pixel, and allows
synchronization between these control signals and the Т-ray acquisition system. This
circuit is the AFX-FF1760 prototyping platform in Figure B.2, with the Virtex-5
LX330 FPGA mounted in the ZIF socket as in Figure B.3(a).

The Virtex-5 LX330 FPGA has the largest number of user-configurable input/output
(I/O) pins, 1,200 I/O pins, among all the Xilinx FPGAs, thus this device can simul-
taneously control all the 1,024 SLM pixels. The FPGAs used for our experiments are
generous donations from the Xilinx University Program (XUP). To mount the FPGA
onto the ZIF socket, first put the FPGA in place with the vacuum handling tool, then
press the socket inward to lock the FPGA into the ball-grid array (BGA) beneath.

The AFX platform downloads the program instructions from the computer to
the FPGA through the USB-JTAG programming cable in Figure B.3(b). These
instructions are written in Verilog programs. The AFX platform connects to the line
driver circuit through IDSD cables manufactured by Samtec, Inc., receives a clock
input from an external signal generator and outputs a synchronization signal to the
Т-ray acquisition system through BNC cables.

Detailed documentations of the Virtex-5 FPGAs and the AFX platform is avail-
able on the Xilinx webpage.

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