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Verilog programming file (.v), which contains the code, and the UCF file (.ucf), which
contains the assignments of the FPGA pins to the program variables. The UCF file
for the SLM control circuit, i.e., the FPGA pin assignments to the SLM pixels, is
fixed and is stored in the control computer. One should not need to reconstruct this
UCF file in the future, but in case of future changes to the circuit, see Section B.3
for the procedure to match the FPGA pins to SLM pixels.
Compilation of a Verilog programs can take several hours sometimes, especially
for programs using many FPGA pins. Once ISE generates the bitstream file (.bit)
after compilation, the FPGA can download and use the bitstream next time without
having to go through compilation procedure again.
More details of the ISE software is available on the Xilinx webpage. Contact the
CMC Lab at Rice University for free download of the ISE software.
B.3 FPGA pin assignments
Arranged in a square array, the pinout description of the Virtex-5 LX330 FPGA
is available on the Xilinx webpage. Notice that the FPGA pinout map has a 180o
rotational symmetry, therefore, two identical line driver boards are designed for each
side of the FPGA circuit.
The labelling for the SLM pixels is as follows: when the SLM board is oriented
such that the white silkscreen box is on the right bottom corner (see Figure B.7), the
pixel on the left top corner is pixel 1. Count downwards in ascending pixel number.
Then, start counting again with the pixel at the top of the second column from the
left as pixel 33. Stay with this counting pattern until reaching pixel 1024 at the
bottom right corner of the SLM.
One may need to use an EXCEL sheet to keep track of the pin assignments from