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one circuit board to another. Here describes the steps to map the pins and the pixels,
i.e., to construct the UCF file:
1. From the schematics of the line driver board in Allegro Design Entry CIS, map
the 512 FPGA pins to the corresponding SHF cable connector pins.
2. From the schematics of the SLM board, map each SHF cable connector pin to
the corresponding PCB bond finger for the SLM chip.
3. Map each Schottky pads on the SLM chip to the corresponding SLM pixel
according to the chip design in Figure 5.5 (mapping between the PCB bond
fingers and the Schottky pads is straightforward).
4. Use this pin-to-pixel mapping to figure out the mapping for the 512 pins on the
other side of the FPGA by its symmetry.
B.4 Line driver circuit
The line driver circuits amplifies each of the 1,024 control signal from the FPGA
circuit from 3V to 16V, since each SLM pixel requires a 16V negative bias for maxi-
mum modulation. The line driver circuit provides +16V to the SLM ohmic contacts
through the SLM board, and switches each of its output control signal between OV
and 16V.
As shown in Figure B.4, the line driver circuit board has a Zener diode and a
fuse for basic circuit protection, a bypass capacitor for a cleaner DC signal, and cable
connectors to connect from the FPGA circuit and to the SLM board. Each line
driver board has 512 outputs, each to an individual SLM pixel. For each SLM pixel,
the circuit performs independent voltage amplification through a bipolar-junction-
transistor (BJT) and two transistors, as shown in Figure B.5. This circuit diagram