The name is absent

exact value of the leakage current involves elaborate expressions. Since such an
exact leakage model does not affect our basic approach, we use following model
presented (n [60].

ʃɪeak = q_ie^^L+^^L2\                          (3.1)

I_leak is the leakage current of a transistor; q₁, q₂, and ⅛ are three constants
that are determined by physical characteristic of the transistor and L is the
gate length of the transistor, q₃ is a small number and q₃L² ≪ q₂L [60]. This
model suggests an exponential relation between the transistor gate length and
the leakage power. Thus, the leakage current approximately has a log-normal
distribution and p_u = φ_up‰ where pɑ and p_u are nominal power and real power
of the gate, respectively, and φ_u = e^“ ; where ≠_u represent variation in transistor
dimension.

Thus, given a combinational circuit C consisting of N logical gates, Pj input
pins, and Pq output pins, each gate g_u, based on its inputs signals b, consumes a
specific power p_guj>∙ Because of the process variation, power consumption of gate
g_u does not equal to its nominal power consumption pθ_uιj,. Rather, it is scaled by
Φu∙

Pgu,b ⁼ Pg_u,bΦu

The scaling factors of gates, φ_u, need to be estimated, whenever it is feasible.

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