Figure 3.2: A simple logic circuit.
Table 3.1: Static power for different input vector combinations.
input vector |
NAND-2 |
NOR-2 |
OO |
0.776 nW |
17.41 nW |
Ol |
10.39 nW |
4.112 nW |
10 |
4.137 nW |
7.581 nW |
11 |
15.15 nW |
3.527 nW |
3.2 Noninvasive tomography
In this section, we detail the full matrix measurement method for noninvasive
gate-level characterization. First, different inputs are applied to the circuit and
the total chip’s leakage current measured for each input. Then, an optimization
problem is solved to find the process variation based on the power measurements.
Consider the simple logic circuit in Figure 3.2. It has 3 inputs and 2 outputs.
The nominal power consumptions of each gate for different inputs are shown
in Table 3.1.The table shows power consumption for 65nm CMOS transistor
26
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