The name is absent

• The transistor model: We have used BSIM4 model for 65nm technology
in the simulations [13]. The BSIM4 model is developed such that it can
accurately model behavior of a transistor in the sub-IOOnm regime.

• Benchmark circuits: We have used a number of MCNC benchmark circuits
in our simulations. The MCNC benchmarks were introduced in 1985 on
magnetic tapes, and they are updated, modified, and enhanced regularly.
The benchmarks are widely used in design automation community (for ex-
ample see [37,54,74]).

• The (^-regularization software: The SPGLl software package [68] is used
for ∕⅛-regularization. The SPGLl uses an iterative approach to solve the
LASSO problem. In each iteration radius of (_i ball is increased until the
convergence. For more details, please see [72].

• The Quadratically constrained quadratic program (QCQP) solver. We
have used SeDuMi (self-dual minimization) software package [61] for (₂-
nimization and the QCQP in Section 3.4. SeDuMi is maintained at the
Advanced Optimization Lab at McMaster University. It can be used to
solve various symmetric cone problems.

• The ATPG tool: PathATPG [77] is used to identify testable paths and to
generate test input pairs for the testable paths. PathATPG is fast ATPG
tool that is based on the SAT-solvers.

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