The name is absent

[49] X. Lu, Z. Li, W. Qiu, D. M. H. Walker, and W. Shi. Longest path selec-
tion for delay test under process variation. In Conference on Asia South
Pacific Design Automation: Electronic Design and Solution Fair, pages 98-
ЮЗ, 2004.

[50] J. Luo, S. Sinha, Q. Su, J. Kawa, and C. Chiang. An ic manufacturing yield
model considering intra-die variations. In Conference on Design Automation,
pages 749-754, 2006.

[51] H. Mangassarian and M. Anis. On statistical timing analysis with inter-
and intra-die variations. In Conference on Design, Automation and Test in
Europe, pages 132-137, 2005.

[52] M. Mani, A. Singh, and M. Orshansky. Joint design-time and post-silicon
minimization of parametric yield loss using adjustable robust optimization.
In International Conference on Computer-Aided Design, pages 19-26, 2006.

[53] K. Meng and R. Joseph. Process variation aware cache leakage management.
In International Symposium on Low Power Electronics and Design, pages
262-267, 2006.

[54] A. Mishchenko, S. Chatterjee, and R. Brayton. Dag-aware aig rewriting a
fresh look at combinational logic synthesis. In Conference on Design Au-
tomation, pages 532-535, 2006.

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