[36] B. Hargreaves, H. Huit, and S. Reda. Intra-die process variations: How
accurately can they be statistically modeled? In Conference on Asia-pacific
Design Automation, pages 524-530, 2008.
[37] J. Hlavicka and P. Fiser. A heuristic method of two-level logic synthesis.
In World Multiconference on Systemics, Cybernetics and Informatics, pages
524-530, 2001.
[38] V. Iyengar, J. Xiong, S. Venkatesan, V. Zolotov, D. Lackey, P. Habitz,
and C. Visweswariah. Variation-aware performance verification using at-
speed structural test and statistical timing. In International Conference on
Computer-Aided Design, pages 405-412, 2007.
[39] V. Khandelwal and A. Srivastava. A general framework for accurate sta-
tistical timing analysis considering correlations. In Conference on Design
Automation, pages 89-94, 2005.
[40] S.-J. Kim, K. Koh, M. L. ans S. Boyd, and D. Gorinevsky. An interior-point
method for large-scale 11-regularized least squares. IEEE Journal of Selected
Topics in Signal Processing, 1(4):606-617, 2007.
[41] K. Lakshmikumar, R. A. Hadaway, and M. Copeland. Characterisation and
modeling of mismatch in mos transistors for precision analog design. IEEE
Journal of Solid-State Circuits, 21(6):1057-1066, 1986.
91
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