[55] T. Mizuno, J. Okumtura, and A. Toriumi. Experimental study of threshold
voltage fluctuation due tostatistical variation of channel dopant number in
mosfet’s. IEEE Transactions on Electron Devices, 41(11):2216-2221, 1994.
[56] A. Murakami, S. Kajihara, T. Sasao, I. Pomeranz, and S. M. Reddy. Selec-
tion of potentially testable path delay faults for test generation. In IEEE
International Test Conference, page 376, 2000.
[57] M. Orshansky, L. Milor, P. Chen, K. Keutzer, and C. Hu. Impact of system-
atic spatial intra-chip gate length variability on performance of high-speed
digital circuits. In International Conference on Computer-Aided Design,
pages 62-67, 2000.
[58] A. Ramalingam, G. Nam, A. Singh, M. Orshansky, S. Nassif, and D. Pan. An
accurate sparse matrix based framework for statistical static timing analy-
sis. In International Conference on Computer-Aided Design, pages 231-236,
2006.
[59] R. Rao, A. Srivastava, D. Blaauw, and D. Sylvester. Statistical estimation
of leakage current considering inter- and intra-die process variation. In In-
ternational Symposium on Low Power Electronics and Design, pages 84-89,
2003.
[60] R. Rao, A. Srivastava, D. Blaauw, and D. Sylvester. Statistical analysis of
subthreshold leakage current for vlsi circuits. IEEE Transactions on Very
94