The name is absent

sured values. They also showed that variations in gate source voltage, Vgs-, are
spatially correlated. They then repeated the procedure for different aspect ra-
tios (W∕L~) and verified the relation between the transistor dimensions and the
threshold voltage variance: σy_th oc (WL_efj)~2. Thus, as the CMOS transistor
dimensions decrease, the fluctuations variance increases.

2.1.2 Variation estimation and modeling

As technology improved and nano-scale CMOS transistors could be fabricated,
process variations became a determining factor. To appreciate how variations
affects the circuit design, one needs a thorough understanding of variation and
its statistical properties in ICs. Several researchers performed measurement and
modeling of the process variations in different CMOS technologies [8,12,16,23,
30,36,43,46,47,50,76,79].

In 2005, Doh et al. [23] experimentally characterized the spatial correlation in
process variations. To do so, they fabricated a 4 × 5 module array in 130nm CMOS
technology. As can be seen in Figure 2.1, each module consisted of 16 patterns of
nMOS and pMOS transistors and an oscillator. Oscillators are standard devices
used to characterize properties of integrated circuits [36]. They consist of a
number of inverters that are connected in a loop circuit. Doh et al. [23] used a
40-pattern ring oscillator (see Figure 2.1). Using this method, they explained the
spatial correlation in variations. Figure 2.2 shows the scatter plot for saturation

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