Figure 2.2: Spatial correlation study by Doh et al [23]. Left: scatter plot of saturation
voltage of ∏MOS transistors. Close modules are strongly correlated. Right:
Spatial correlation decreases as distance between modules increases.
that spatial correlation increases after a specific distance, but they do not have
any argument that interprets the experimental results. Their method is inva-
sive and expensive in time and equipment, making it very hard to characterize
variations in a large number of ICs using ELM.
Zhao et al. [79] used a transistor array to study the process variation. They
used the test chip that was designed and fabricated by Agraval et al. [7]. The test
structure was specifically designed to determine the local variation in transistors.
The dimension of the test structure was 125μm × 110μm and it consisted of IOOO
columns and 96 rows. They used Level Sensitive Scan Device (LSSD) latch banks
in the structure to allow addressing each transistor uniquely. They determined
current voltage characteristics of all transistors. The observed variations were
thought to be a result of threshold voltage and gate-length variations. They also
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