The name is absent

None of these methods provides a fast and practical method for variation
estimation. They are either invasive, that is destructive, and expensive in terms
of the time and equipment cost, or they rely on addition of on-chip oscillators
for variation sensing. We introduce a fast, non-invasive, and inexpensive method
to estimate the variation. Only a small number of power or delay measurements
are used to characterize the gate-level post-silicon variations.

2.1.3 Effects of variations on the design

Process variations have considerable effects on chip properties [2-6,9,19,21,26,
33,44,51,57]. For example, they can seriously affect timing [14,17,19,39,49,
51,57,58,78]. In statistical static timing analysis (SSTA), researchers try to
find signal propagation delays on the critical paths in a circuit. Most of the
proposed solutions are particularly interested in finding the statistical distribution
of the maximum propagation delay. Orshansky et al. [57] found that in 180nm
technology not considering process variation might cause a 25% timing error.
Choi et al. [19] estimated path delays under process variation and proposed a
new sizing algorithm. Their proposed method performed up to 19% better than
the worst case analysis. Mangassarian et al. [51] found the delay probability
distribution function (pdf) of the critical paths and sorted them. Based on sorted
pdf of path delay, they proposed a statistical timing analysis that is about 30%
better than the worst case analysis.

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