Above methods are pre-silicon models that a specific variations distribution
is assumed on the IC. Cline et al. [20] analyzed impacts of the variations models
on SSTA methods. They used real measurement data to fit the models such
ð that the correlation decreases as distance between two gates increases. Then,
they compared the SSTA methods of the models with the static timing analysis
(STÀ). They showed that correlation models for the SSTA should follow the
specific process variations in the IC. Otherwise, the performance of the SSTA
would degrade.
Liu et al. [48] introduced an SSTA method using post-silicon measurements
and optimizations. They combined post-silicon measurements with the existing
pre-silicon models for the variations. Thus, they constructed a specific model for
each die. The proposed method could decrease the standard deviation by 83.5%
compared to the traditional post-silicon SSTA techniques.
Process variations affect the performance of pipelined circuits as well.
Pipelined circuits consist of a number of sequential stages. To increase the oper-
ating frequency, one needs stages with small delays, but the slowest stage is the
system’s bottleneck. In the presence of variations, delay of each gate is randomly
distributed according to a some pdf and it is not possible to exactly determine
the slowest stage [21]. Datta et al. [21] showed that considering variations can
result in a 9% improvement of design yield. Eisele et al. [26] showed that, in
180nm CMOS technology, variation might cause a 10% reduction in the operat-
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