measurements on a set of testable paths, the goal is not characterizing the delay
variations. In the circuit testing, only defected gates are interested while the goal
of our method is to characterize the delay variations of the gates.
Thus, the process variations affect many different properties of a manufactured
IC and they can not be ignored anymore. The previously described methods for
variation estimation are expensive and cannot be extended for a legacy IC.
2.2 Preliminaries
2.2.1 Variation model
Process variations can be generally described as the sum of systematic variations
and random variations. The systematic variations have a deterministic pattern
resulting from physical imperfection in the manufacturing process. For example,
mask imperfections result in systematic variations in the chip. Because of their
deterministic source, systematic variations can potentially be known beforehand
[76]. The systematic variations of a specific logical gate u, denoted by ψfl, are
usually linearly modeled [47],
≠u = aO + a1xu + a2yu:
where ɑɑ, «i and a2 are the model parameters and (xu, yu) is physical location of
the gate on the IC.
18
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