ing frequency.
Leakage current of an IC also changes with process variation [3,5,11,59,60].
Agarwal et al. [5] proposed a method to model IC leakage current distribution.
They showed that in 50nm CMOS technology the coefficient of variation of the
total current might vary between 0.17 to 0.98.
2.1.4 Testing
The goal of the IC testing is finding the defective gates in the circuit [56,64,65].
The test might be a functional test or a delay test. In the functional test, the
logical functionality of the gates is tested. The delay test ensures that the delays
of all gates satisfy a number of specific constraints.
Finding a set of testable paths is the most important task in the testing.
Sharma et al. [65] introduced a technique to construct a small basis path set
that cover all gates. They proposed automatic test pattern generation (ATPG)
techniques to identify the longest testable path through each gate. Thus, they
could detect any defect in the circuits using delay measurements.
Murakami et al. [56] introduced a method to recognize Untestable paths. Their
method was based on the logical necessity conditions that should be satisfied
for a path to be testable. Knowing the necessity conditions, they proposed an
algorithm to find the longest testable path trough each gate.
Although, similar to our method, the circuit testing is based on the delay
17
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