ship between the capacitance and the random variations, and they numerically
showed how variations affect the capacitance. For example, they showed that a
Gaussian random fluctuation with variance 0.1μm in a capacitor with edge length
50μm causes only 0.036% difference in capacitance. Their results indicate that,
in early CMOS capacitors, the effects of the random variations were negligible.
Lakshmikumar et al. [41] in 1982 proposed a method to predict the current
mismatch (intra-die) of the transistors on an integrated circuit. Since only the
relative dimensions of transistors are important in analog design, the impacts of
global variations (inter-die) were not analyzed in this work. They had two main
missions in the paper. First, sources of variations were determined and a model
was fitted to the measurement data. In other words, they tried to predict the
systematic part of the variation. Second, they constructed an analytical relation
between the current mismatch and transistor dimensions. Thus, the predicted
current mismatch could be transformed into dimension variations. Knowing the
variation in dimensions helps designing more precise analog circuits. However,
random variations were not considered. This, the total variations could not be
predicted.
In 1995, Eisele et al. [27] used a 10 × 10 transistor array to study intra-
die variations in manufactured ICs. Their addressing scheme allowed individual
transistor selection, meaning, they could characterize each transistor separately.
After finding Vgs of all transistors, a normal distribution was fitted to the mea-