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gate-level characteristics estimation more than 100%, while on the b9 benchmark,
the improvement is only 10%.

A number of applications can enjoy non-invasive post-silicon characterization.
They include post-silicon optimization, manufacturing process characterization,
simulation improvement and IC identification.

The new aspect of this thesis are as follows:

• We propose a method for post-silicon gate-level characterization for both
power and delay frameworks, that only uses non-invasive measurements. In
contrast to variation measurement methods based on the ring oscillators,
our method works for a general combinatorial IC.

• For the first time, we represent post-silicon variations in a sparse domain.
Even though the spatial correlation in the variations is widely studied before
[23,30,79], it is the first time that is used for post-silicon optimization.
We experimentally determine which wavelet basis results in the sparsest
representation.

• We use the theory of compressive sensing to estimate the variations with
a small number of measurements. We use the wavelet basis to sparsely
represent delay and power variations.

• We analyze the regularization factor in ^!-regularization and introduce a
method to estimate the optimal regularization factor.

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