The name is absent

lays [63]. The same approach as in post-silicon leakage characterization is used
for gate level delay variation characterization. However, in contrast to the power
variations, the variations in delay are additive and they are linear functions of the
CMOS dimensions. We use HSPICE simulation to find linear relations between
transistor variations and delay variations in various gates. However, in the delay
framework, the from and the construction of the system of linear equations is dif-
ferent from the power framework. In the delay framework, one can only measure
the delay of the signal propagation on specific paths that start form a primary
input and end at a primary output. Such paths are called sensitizable (testable)
paths [64,65]. We use the testable basis selection method in [65] to find a set of
sensitizable basis paths for a circuit. Then, using the linear relationship between
transistor dimensions and the gate delays, we construct a system of linear equa-
tions with variations as the unknown variables. Again, we can use traditional
^-minimization or ^-regularization (compressive sensing) to estimate the gate
level timing characteristics.

We evaluate performance of the proposed methods for both delay and power
frameworks on a number of circuits from the MCNC benchmark suits. Results
indicate that ^-regularization method can estimate the variations much more
accurately than the traditional ^-minimization. However, performance of the
^ι-regularization method depends on the circuit topology. For example, in delay
framework, the ^!-regularization method on the C499 benchmark circuit improves

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