The name is absent

Dimensions of a manufactured CMOS transistor is not exactly as it was de-
signed. If one measures the dimensions of the manufactured transistors, there
are some variations from the design specifications. This phenomenon is called
manufacturing variation. Imperfection in manufacturing tools is the main con-
tributor to systematic process variations. For example, because of the limitations
on the minimum wavelength of the laser etching the mask [45], masks that are
used in the manufacturing are not totally similar and symmetric. Thus, the tran-
sistors dimensions depend on the specific mask used in the manufacturing process
and the transistors’ location on the mask. Another reason for the manufactur-
ing variations is uncontrollable physical parameters of the manufacturing process
(random variations). Because it is not possible to control strictly the physical
environment of the fabrication, manufacturing two ICs with the same mask does
not result in the same variations.

Process variations can dramatically affect properties of manufactured ICs.
Statistical static timing analysis (SSTA) statistical power analysis are two exam-
ples of the techniques that considers variations for pre-silicop optimizations. In
SSTA, the goal is to find the longest path delay in the circuit. Because of the
nondeterministic behavior of variations, no single path always elicits the longest
delay. Thus, path delays should be statistically modeled and then the longest
delay of the circuit is determined with a specific confidence interval. Orshansky
et al. [57] showed that variations might cause up to 25% error in timing analysis.

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