List of Figures
2.1 Design structure used by Doh et al. [23]............... 11
2.2 Spatial correlation study by Doh et al [23].............. 12
2.3 Measured process variation in a wafer [30].............. 13
2.4 Variation on four test chips...................... 14
3.1 Global flow of the power tomography................. 25
3.2 A simple logic circuit.......................... 26
3.3 Number of independent measurement vectors............ 29
3.4 The power variation and its sparse wavelet transform........ 30
3.5 Sorted wavelet coefficients (power).................. 31
3.6 Gates are not placed on regular grids................. 33
3.7 Irregular wavelet transformation................... 34
4.1 Globalflowofthedelaytomography................. 40
4.2 A sensitizable path from an input to the output.......... 40
4.3 Delay variations and their wavelet transform............. 47
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