In the statistical power analysis, it is also shown that under variations the ratio
of standard deviation to the mean of the total current might varies between 0.17
to 0.98 [5]. However, pre-silicon optimizations, such as SSTA, have some limita-
tions: the statistical characterizations of variations are not precisely determined
and they might vary on different chips.
A number of post-silicon variations characterization methods have recently
introduced [23,30,36,79]. Friedberg et al. [30] used electrical linewidth metrology
(ELM) to measure variations of chips’ dimensions on a wafer. They exhaustively
measured the variations of all the transistors. Hargreaves et al. [36] introduced a
post-silicon characterization method using ring oscillators. They put a number of
ring oscillators in different locations on an IC. Then, they measured the frequency
of each ring oscillator. Frequencies of the oscillators represent variations across
the IC. The mentioned methods are either expensive [30] or design specific [36].
We propose a fast, non-invasive, and inexpensive method for gate level post-
silicon characterization using power and delay measurements. In the power frame-
work, we first explain how the nominal leakage power consumptions of a logic gate
are multiplied by a scaling factor due to process variations. The scaling factor
indicates the ratio of the gate leakage to its expected value. Then, we show that
measuring the total power consumption for each circuit input enforces a linear
constraint on scaling factors. Feeding the circuit with different input vectors
and measuring the total power for each input vector leads to a system of Iin-