An Efficient Circulant MIMO Equalizer for CDMA Downlink: Algorithm and VLSI Architecture

Yuanbin Guo et al.

-*- LMS

-O- CG, iter. = 3

∙∙V∙ CG, iter. = 5

FFT-based

DI

Figure 11: BER performance of 2 × 2 in Pedestrian-B channel case 2: K = 10 codes; K = 10, G = 16, Lh = 6, T = 2, M = 2, and F = 10.

-*- LMS                        FFT-based

-O- CG, iter. = 5               -→- DMI

Figure 12: BER performance of 4 × 4 in Pedestrian-A channel; K = 12, G = 16, Lh = 3, T = 4, M = 4, and F = 10.

is presented in [13].

However, this type of SoC design space exploration is
very time consuming because the current standard trial-
and-optimize approaches apply hand-coded VHDL/Verilog
or graphical schematic tools. In this section, we present
a Catapult C-based HLS methodology [26] to explore the
VLSI architecture space extensively in terms of the area/time
tradeoff. This is enabled with high-level architecture and re-
source constraints. Synthesizable RTL is generated from a
fixed-point C/C++ level design and imported to the graph-
ical tools for module binding. The proposed procedure for
implementing an algorithm to the SoC hardware is shown
in Figure 14. The number of FUs is assigned according to
the time/area constraints. Software resources such as regis-
ters and arrays are mapped to hardware components and re-
quired finite-state machines (FSMs) necessary for accessing
these resources are generated. In this way, we can study sev-
eral architecture solutions efficiently. In the next step of the
design flow, the generated RTL is imported into the HDL en-
vironment and integrated with other modules of the system,

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